Digital implementation of RC low pass filter

Posted by Krishna Pillai

December 2, 2007

Thanks to the nice article from Xilinx TechXclusives [XLNX-TECH], let us try to understand the probable digital implementation of resistor-capacitor based low pass filter. This article used to available on Xilinx website (here), but seems it has been removed.

Consider a simple RC filter shown in the figure below. Assuming that there is no load across the capacitor, the capacitor charges and discharges through the resistor path.

RC low pass filter

Figure: RC low pass filter

$v_i$ is the voltage at the input of resistor and

$v_o$ is the voltage at the output.

From capacitor theory, the charge in the capacitor is $Q=CV=\int i dt$ , where

$C$ is the capacitance

$V$ is the voltage and

$i$ is the constant current flowing for short duration of time $dt$ .

With the input voltage $v_i$ is greater than output voltage $v_o$ , resulting in current $i$ flowing through the resistor $R$ , where $i$

$i=\frac{(v_i-v_o)}{R}$ .

When this current flows into the capacitor for a short time $dt$ , the capacitor will charge and the voltage across the capacitor increases to

$v^'_o = v_o + \frac{1}{C}idt = v_o + \frac{1}{RC}(v_i-v_o)dt$ , where

$v^'_o$ is the new value of output voltage.

Digital Implementation

The above equation seems to be convenient for digital implementation as shown in the equation below:

$y[n] = y[n-1] + k(x[n-1]-y[n-1])$

where,

$k=\frac{1}{RC}dt$ ,

$y[n]$ is $v^'_o$ ,

$y[n-1]$ is $v_o$ and

$x[n-1]$ is $v_i$ .

The transfer function of the above equation is

$H(z) = \frac{kz^{-1}}{1-(1-k)z^{-1}}$ .

Simulation model

Script for plotting the frequency and step response of a digital RC low pass filter.

Click here to download.

Frequency response of a digital RC low pass filter

Figure: Frequency response of the digital implementation of RC low pass filter

Step response of a digital RC low pass filter

Figure: Step response of the digital implementation of RC low pass filter

Observations

1. As expected, lower the value of k, tighter is the frequency response and slower is the settling time. This is in synch with analog RC implementation, where a higher value of R and C suggests that the capacitor takes more time to charge/discharge (Note that k is inversely proportional to RC).

2. To facilitate simpler digital implementations not involving multipliers, the value of k can be chosen to be a power of 2.

References

[XLNX-TECH] Xilinx TechXclusives: Digitally Removing a DC Offset (or “DSP Without Math?”), By Ken Chapman Senior Staff Engineer, Applications Specialist, Xilinx UK. This article used to available on Xilinx website (here), but seems it has been removed. The link from Google cache available here (Accessed on 2 December 2007)

Hope this helps.

Krishna

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